Testable scan path circuit operable with multi-phase clock

Details Testable scan path circuit operable with multi-phase clock Testable scan path circuit operable with multi-phase clock

1993-11-18

1996-05-21

Cosimano, Edward R.

Excavating

371 251, 324 731, 307404, 307406, G01R 3128, G06F 1100

Patent

active

055197140

ABSTRACT:
A logic circuit associated with a scan path circuit includes at least one clock controller and at least one scan flipflop. The clock controller includes a first control gate receiving a clock signal and a scan mode signal and configured to maintain its output at a fixed value when the scan mode signal is active, a second control gate receiving an output of the first control gate and a first test clock signal for generating a first enable signal, and a third control gate receiving an output of the second control gate and a second test clock signal for generating a second enable signal. The scan flipflop includes a selector having a pair of inputs receiving a data input signal and a scan input signal, respectively, and also having a selection input receiving the scan mode signal so that when the scan mode signal is active, the scan input signal is selected, and when the scan mode signal is inactive, the data input signal is selected. A first latch circuit receives an output of the selector at its data input and the first enable signal at its enable terminal. A second latch circuit receives an output of the first latch circuit at its data input and the second enable signal at its enable terminal.

REFERENCES:
patent: 4649539 (1987-03-01), Crain et al.
patent: 4860290 (1989-08-01), Daniels et al.
patent: 4942577 (1990-07-01), Ozaki
patent: 5021774 (1991-06-01), Ohwada et al.
patent: 5043986 (1991-08-01), Agrawal et al.
patent: 5130646 (1992-07-01), Kojima
patent: 5260946 (1993-11-01), Nunally

Affiliated with

Also associated with

Rating

Testable scan path circuit operable with multi-phase clock does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Testable scan path circuit operable with multi-phase clock, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testable scan path circuit operable with multi-phase clock will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2044951