Method of dividing a pipelined stage into two stages in a comput

Details Method of dividing a pipelined stage into two stages in a comput Method of dividing a pipelined stage into two stages in a comput

1993-07-09

1996-05-21

Trans, Vincent N.

Boots, shoes, and leggings

364491, 395500, G06F 1750, G06F 938

Patent

active

055196268

ABSTRACT:
A method, practiced in a CAD system, of automatically dividing a pipeline stage into two. A designer specifies a desired signal processing time for division of the stage. The CAD system automatically identifies circuit locations that meet the specified signal processing time and divides the stage at those points, providing new netlists for the new stages.

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Prabhu, Usha and Panngle, Barry M.; "Superpipelined Control and Data Path Synthesis" 29th ACM/IEEE Design Automation Conference, 1992, pp. 638-643.
Kaiser et al., "Risp: A Digital Signal Processor Architecture with Reduced Instruction Set Tailored to Wave Digital Filters", IEEE 92, pp. 32-35.
Hung et al., "High-Level Synthesis with Pin Constraints for Multiple-Chip Designs", IEEE 92, pp. 231-234.

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