Structure of a channel write/erase flash memory cell

Details Structure of a channel write/erase flash memory cell Structure of a channel write/erase flash memory cell

1998-11-05

2000-07-18

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 36518527, 36518528, 36518526, 36518502, G11C 1604

Patent

active

060916443

ABSTRACT:
A channel write/erase flash memory cell structure together with its method of manufacture and mode of operation. The flash memory cell structure is formed by implanting P-type ions into a substrate to form a shallow-doped region, and then implanting N-type ions to form the drain terminal of the flash memory cell. Next, a deep-doped region that acts as a P-well is formed underneath the drain terminal. Method of manufacturing the channel write/erase memory cell and its mode of operation is also discussed.

REFERENCES:
patent: 5268318 (1993-12-01), Harari
patent: 5627394 (1997-05-01), Chang et al.
patent: 5631485 (1997-05-01), Wei et al.
patent: 5696401 (1997-12-01), Mizuno et al.

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