Multi-bank memory with word-line banking, bit-line banking and I

Details Multi-bank memory with word-line banking, bit-line banking and I Multi-bank memory with word-line banking, bit-line banking and I

1999-07-06

2000-07-18

Tran, Andrew Q.

Static information storage and retrieval

Interconnection arrangements

365 72, 365 51, 36523003, 36523004, 36523005, 36523006, 36518902, G11C 506

Patent

active

060916206

ABSTRACT:
A multiple bank memory array includes a combined memory array, an X-decoder, a first word-line driver, a second word-line driver, a reference column, a Y-multiplexer and pre-charging circuit, a sense amplifier and input/output circuit, and control and pre-coding logic. Signals are received and applied to the combined memory array and the other components via the control and pre-decode logic and the input/output circuit. The control and pre-decode logic receives control signals to control and address the combined memory array, and uses a single bit for two dimensional decoding. This architecture for multiple bank memory cell arrays a novel technique for word-line banking using tilable strap cells in a first embodiment that provides a combined array, does not require routing and eliminates redundant reference columns. The multiple bank memory array in a second embodiment also includes a novel technique for bit-line banking that eliminates sense amplifiers, provides for tilable connection between the sense amplifiers and the input/output circuit, and maintains an optimum aspect ratio. In a third embodiment, the invention provides a tilable I/O interconnect structure for use on another level of banking. The banking concepts provided in the present invention are independent of the type of memory cell and applicable to all varieties of memory cells.

REFERENCES:
patent: 5500822 (1996-03-01), Han
patent: 5506816 (1996-04-01), Hirose et al.

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