Method for arranging tree-type clock signal distributing circuit

Details Method for arranging tree-type clock signal distributing circuit Method for arranging tree-type clock signal distributing circuit

1994-11-10

1996-05-21

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327293, 364491, 364489, 395550, H03K 104

Patent

active

055193510

ABSTRACT:
In a synchronous integrated circuit including a plurality of functional blocks, the plurality of functional blocks are divided into a plurality of segments. Each of the segments is further divided into classes whose number is dependent upon the density of the functional blocks within each of the segments. A distribution of the functional blocks allocated to one class is homogeneous within the segment to which the class belongs, and one clock buffer is allocated at a substantial center position of the functional blocks within the class.

REFERENCES:
patent: 4812684 (1978-03-01), Yamagiwa et al.
patent: 5293626 (1994-03-01), Priest et al.
patent: 5293627 (1994-08-01), Kato et al.
patent: 5361277 (1994-11-01), Grover
patent: 5410491 (1995-04-01), Minami
Kimoto et al., "Open CAD Clock Tree Synthesis", NEC Technicasl Bulletin, vo. 45, No. 8, (192), p. 16-20.

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