Multi-phase test point insertion for built-in self test of integ

Details Multi-phase test point insertion for built-in self test of integ Multi-phase test point insertion for built-in self test of integ

1996-07-01

1998-04-07

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057373400

ABSTRACT:
Method and apparatus for providing high quality Built-in-Self-Test (BIST) of integrated circuits, while guaranteeing convergence and reducing area-overhead and power dissipation during test mode. A divide and conquer approach is used to partition the test into multiple phases during which a number of test patterns are applied to a circuit under test (CUT). The design of each phase (the selection of control and observation points) is guided by a progressively reduced list of undetected faults. Within a phase, a set of control points maximally contributing to the fault coverage achieved so far is identified using a unique probabilistic fault simulation (PFS) technique. The PFS technique accurately computes a propagation profile of the circuit and uses it to determine the impact of a new control point in the presence of control points selected so far. In this manner, in each new phase a group of control points, driven by fixed values and operating synergistically, is enabled. Observation points are selected in a similar fashion to further enhance the fault coverage. The sets of control and observation points are then inserted into the circuit under test and a new, reduced list of undetected faults is determined through exact fault simulation. This process is iterative and continues until the number of undetected faults is less than or equal to an acceptable threshold, a pre-specified number of control and observation points have been inserted, or the maximum number of specified test phases has been reached.

REFERENCES:
patent: 4701920 (1987-10-01), Resnick et al.
patent: 4918378 (1990-04-01), Katircioglu et al.
patent: 4949341 (1990-08-01), Lopez et al.
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 5230000 (1993-07-01), Mozingo et al.
patent: 5258985 (1993-11-01), Spence et al.
patent: 5383195 (1995-01-01), Spence et al.
patent: 5414716 (1995-05-01), Bershteyn
patent: 5428625 (1995-06-01), Dekker
Test Point Placement to Simplify Fault Detection; Hayes et al.; IEEE Transactions on Computers, vol. C-23, No. 7, pp. 727-735 (Jul. 1974).
On Testability Analysis of Combinational Networks; Franc Brglez; ISCAS '84; pp. 221-225 (1984).
Statistical Fault Analysis; Jain et al.; IEEE Design & Test; pp. 38-44 (Feb. 1985).
Predict -Probabilistic Estimation of Digital Circuit Testability; Seth et al.; IEEE, pp. 220-225 (1985).
A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation; Waicukauski et al; 1985 International Test Conference; Paper No. 21.3; pp. 779-784 (1985).
Protest: A Tool For Prababilistic Testability Analysis; Wunderlich; 22nd Design Automation Conference; Paper 14.3; pp. 204-211; (1985).
Random Pattern Testability by Fast Fault Simulation Briers et al.; IEEE 1986 International Test Conference; paper 9.5 pp. 274-281 (1986).
A Dynamic Programming Approach to the Test Point Insertion Problem; Krishnamurthy; 24th ACM/IEEE Design Automation Conference; Paper 36.3, pp. 695-705 (1987).
Synthesis of Pseudo-Random Pattern Testable Designs; Iyengar et al.; 1989 International Test Conference; Paper No. 22.2, pp. 501-508 (1989).
An Observability Enhancement Approach for Improved Testability and At-Speed Test; Rudnick et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol. 13, No. 8, pp. 1051-1056 (Aug. 1994).
DFTGEN User's Guide, Digital Equipment Corp., Jul. 1995.
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST; Kwang-Ting (Tim) Cheng et al.; International Test Conference; Paper 23.1: 506-514 (1995).
Test Point Insertion for Scan-Based BIST, Bernhard H. Seiss, Pieter M. Trouborst, Michael H. Schulz, Published before Jul. 1, 1996.

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