Device for reducing the redundancy in blocks of digital video da

Details Device for reducing the redundancy in blocks of digital video da Device for reducing the redundancy in blocks of digital video da

1990-03-06

1991-04-09

Kostak, Victor R.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358136, 341200, H04N 713

Patent

active

050069306

ABSTRACT:
A converter processes a digital video signal according to a known redundancy reducing algorithm executed on successive block for each frame or field and generates a transformed signal which is applied to a quantizer adapted to generate a quantized signal at preset transition levels on opposed sides of the zero, including the zero ( . . . ,-3,-2,-1, 0, 1, 2, 3, . . . ). The quantized signal is processed by a processor, adapted to determine the block length and the consecutive zero sequences along a preset scanning order, and to output a symbolic signal constituted by symbols indicating the quantization levels of the non-null data, the zero sequences and a symbol indicating the block end. The symbolic signal is applied to a variable length VLC encoder, adapted to encode data according to a preset designation law for generating a signal which is applied to a transmission buffer. The quantized signal generated by the quantizer further includes two ambiguous levels (x1 and x-1) at input values falling within respective preset intermediate ranges respectively between the zero level and the first positive level and between the zero level and the first negative level; the processor transforms each of the ambiguous levels respectively into a first positive level and a first negative level if the preceding and subsequent input values are both non-null and non-ambiguous, and transforms the ambiguous level into zero in all other cases.

REFERENCES:
patent: 4743967 (1988-05-01), Takenaka et al.
patent: 4802004 (1989-01-01), Matsumoto et al.
patent: 4875095 (1989-10-01), Matsumoto et al.

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