Method for forming metal interconnection of semiconductor device

Details Method for forming metal interconnection of semiconductor device Method for forming metal interconnection of semiconductor device

1995-07-07

1996-05-21

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437192, 437190, 216 41, H01L 2144

Patent

active

055189636

ABSTRACT:
A method for forming a metal interconnection capable of minimizing plasma etching damage on a metal layer having a relatively higher step when forming a via hole. The method for forming a metal interconnection of a semiconductor device where a first metal layer and a first insulating layer are formed and a via hole is formed in the first insulating layer, thereby connecting the first metal layer to a second metal layer which is located on a layer different from the first metal layer, comprising; a first step of forming a second insulating layer having the same size as that of the via hole in the first insulating layer over the first metal layer; a second step of forming an etching barrier to cover the second insulating layer for formation of the pattern of the first metal layer; a third step of etching the first insulating layer and the first metal layer using the etching barrier as an etching mask; a fourth step of forming a third insulating layer over the resultant structure formed by the first step to the third step to planarize said resultant structure, and etching the third insulating layer to expose the second insulating layer; a fifth step of removing the exposed second insulating layer and the portion of the first insulating layer exposed by the removal of the second insulating layer; and a sixth step of forming the second metal layer.

REFERENCES:
patent: 4410622 (1983-10-01), Dalal et al.
patent: 4954423 (1990-09-01), McMann et al.
patent: 5380679 (1995-01-01), Kano
patent: 5436199 (1995-07-01), Brighton

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