Electrical isolation method for devices made on SOI wafer

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437 35, 437 40, 437 41, 148DIG150, H04L 2176

Patent

active

055189490

ABSTRACT:
The present invention is related to an isolation method for SOI (Silicon on Insulator) devices on an SOI wafer having a silicon substrate, a buried dielectric layer formed on the silicon substrate and a silicon film layer formed on the buried dielectric layer. The method includes steps of: a) growing a first oxide layer on the SOI wafer; b) depositing a silicon nitride layer on the first oxide layer; c) defining a photoresist pattern on the resulting product to sere as a mask; d) etching portions of the silicon nitride layer, the first oxide layer and the silicon film layer according to the photoresist mask to obtain a silicon-film island region; e) laterally etching the silicon nitride layer above the silicon-film island region with an isotropic nitride etchant to cause a horizontal recess between the photoresist mask and the first oxide layer; f) removing the photoresist mask; g) growing a second oxide layer over side walls of the silicon-film island region to passirate defects over the side walls; h) proceeding a lapse angle ion-implantation to the side walls of the silicon-film island region; i) depositing a third oxide layer on the resulting product; j) etching back the third oxide layer to have the silicon nitride layer above the silicon-film island region exposed and to form oxide side-wall spacers against the side walls of the silicon-film island region; k) removing the silicon nitride layer; and l) etching the first oxide layer on the silicon-film island region and the top potions of the oxide side-wall spacers smoothened simultaneously.

REFERENCES:
patent: 4753896 (1988-06-01), Matloubian
patent: 4755481 (1988-07-01), Faraone
patent: 4950618 (1990-08-01), Sundaresan et al.
patent: 5034789 (1991-07-01), Black
patent: 5346839 (1994-09-01), Sundaresan

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Electrical isolation method for devices made on SOI wafer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrical isolation method for devices made on SOI wafer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrical isolation method for devices made on SOI wafer will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2037632

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.