Process for fabricating a CMOS transistor having high-voltage me

Details Process for fabricating a CMOS transistor having high-voltage me Process for fabricating a CMOS transistor having high-voltage me

1995-05-08

1996-05-21

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 44, 437 56, 437 58, 437 69, 148DIG82, H01L 218238

Patent

active

055189385

ABSTRACT:
A process for fabricating a high-voltage metal-gate CMOS transistor is disclosed. The CMOS transistor comprises a pair of complementary NMOS and PMOS transistors. The CMOS transistor is fabricated on an semiconductor substrate of a first conductivity type, which has a well region of a second conductivity type therein; therefore, the PMOS and NMOS are fabricated onto the substrate or well region, separately. It can be understood that use of the opening prepared in the initial, and, the only primary shielding layer for the location of the source/drain regions of both the NMOS and PMOS transistors, comprises the key to the precision alignment, and to the dimensional symmetry of the transistors fabricated. This is because that the subsequent fabrication procedural steps after the formation of the shielding layer with the set openings, including all the deposition, the ion implantation, and the etching, etc., all utilize the single positioned reference as set up in the initial shielding layer, with its initial openings defining the locations of the source/drain, as well as the gate regions for the transistors. This allows to ensure the uniformity of the electrical characteristics of the transistor device as fabricated, in each of the process batches. Furthermore, the relatively flat surface of the fabricated transistor pair, after the metal-gate and contacts are formed, also helps to assist the progress of the subsequent device fabrication procedures.

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patent: 5342803 (1994-08-01), Shimoji
patent: 5376568 (1994-12-01), Yang

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