dRAM cell and array

Details dRAM cell and array dRAM cell and array

1984-09-24

1987-07-28

Edlow, Martin H.

357 59, 357 55, 357 41, H01L 2978, H01L 2904, H01L 2906, H01L 2702

Patent

active

046834869

ABSTRACT:
A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel, and drain and one capacitor plate are formed in a layer of material inserted into the trench and insulated from the substrate; the gate and other capacitor plate are formed in the substrate trench sidewall. In preferred embodiments bit lines on the substrate surface connect to the inserted layer, and word lines on the substrate surface are formed as diffusions in the substrate which also form the gate. The trenches and cells are formed in the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.

REFERENCES:
patent: 4199772 (1980-04-01), Natori et al.
patent: 4353086 (1982-10-01), Jaccodine et al.
patent: 4396930 (1983-08-01), Mizutani
patent: 4462040 (1984-07-01), Ho et al.
Chang et al., IBM Technical Disc. Bulletin, No. 8B, vol. 22, pp. 3683-3687.

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