Technique for increasing gate-drain breakdown voltage of ion-imp

Details Technique for increasing gate-drain breakdown voltage of ion-imp Technique for increasing gate-drain breakdown voltage of ion-imp

1985-12-27

1987-07-28

Wojciechowicz, Edward J.

357 15, 357 91, H01L 2980

Patent

active

046834850

ABSTRACT:
The gate-drain breakdown voltage of an ion-implanted JFET is effectively increased by forming the top gate region through two sequential implantation steps to result in respective pockets of different impurity concentration. The deeper pocket (defining the top gate-drain PN junction) has a low impurity concentration profile thereby increasing the breakdown voltage of the gate-drain PN junction, while a second higher impurity concentration implant, which forms a pocket in the first implanted pocket of the top gate, provides the necessary charge carrier concentration to prevent the top gate from becoming fully depleted when the device is biased near pinch-off.

REFERENCES:
patent: 3681668 (1972-08-01), Kobayashi
patent: 4143386 (1979-03-01), Kaiser

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