Method and apparatus for compensating a solid state attenuator

Details Method and apparatus for compensating a solid state attenuator Method and apparatus for compensating a solid state attenuator

1990-01-23

1991-04-09

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307264, 333 81R, H03K 508, H01P 122

Patent

active

050067354

ABSTRACT:
A binarily weighted FET attenuator implemented in integrated form. The resistance of the vertical branches to the horizontal branches is at a ratio of 2:1. Each vertical branch includes a FET switch for switching between ground and a summing amplifier and each horizontal branch includes a FET permanently biased to conduct. Thus, variations in the value of r.sub.on, the resistance of each FET when conducting, due to fabrication process and temperature are compensated for due to the presence of FETs in both the vertical and horizontal legs of the attenuator.

REFERENCES:
patent: 4366396 (1982-12-01), Rosler et al.
patent: 4468607 (1984-08-01), Tanaka et al.
patent: 4523161 (1985-06-01), Miles

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