Driver circuit for a three-state gate array using low driving cu

Details Driver circuit for a three-state gate array using low driving cu Driver circuit for a three-state gate array using low driving cu

1984-07-19

1987-07-28

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307456, 307549, 307270, H03K 19086, H03K 1726, H03K 1760

Patent

active

046833838

ABSTRACT:
A driver circuit for simultaneously setting up a plurality of output buffers of a 3-stage gate array into and out of a floating state using low control current. A buffer driver transistor is provided for each output buffer with the primary control path of that transistor introducing a control circuit to the respected output buffer. A common driver transistor has a primary current path which provides a control signal to the control electrodes of a plurality of buffer driver transistors. Clamp means are provided for discharging the conductor means to ground upon turn-off of the common driver transistor. Clamp means preferably includes a clamp transistor having a primary current path coupled between the conductor means and ground and having a differentiator coupled to the common driver transistor for detecting the leading edge of turn-off of that transistor and in response thereto momentarily, dynamically turning on the clamp transistor to couple the conductor means to ground and thereby discharge any effective capacitance of the conductor means to ground.

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patent: 4322640 (1982-03-01), Fukushima et al.
patent: 4467223 (1984-08-01), Neely
patent: 4481430 (1984-11-01), Houk et al.
patent: 4529895 (1985-07-01), Garverick et al.
Mullgrav, Jr., "Three-State Feature FET-Level Push-Pull Driver", IBM-TDB, vol. 26, No. 7A, pp. 3253-3254, 12/1983.
"The TTL Data Book for Design Engineer", p. 6-35, published by Texas Instruments, 1976 edition.

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