Microprogram memory with page addressing and address decode in m

Details Microprogram memory with page addressing and address decode in m Microprogram memory with page addressing and address decode in m

1981-06-02

1984-05-01

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 922

Patent

active

044465173

ABSTRACT:
A microprogram control system in which the processing speed of a microprogram is increased and the capacity of the microprogram memory is reduced. The decoder previously provided in microprogram control systems to decode the contents of the instruction register are omitted to attain an increased processing speed and the instruction decoding function is integrated into the microprogram memory to attain a general purpose control system. The microprogram memory is divided into pages each consisting of a plurality of words, so that an arbitrary page can be designated as an instruction decode area under the control of the microprogram. Error checking in the system is facilitated by providing a check function for readout error, and a short word memory device is used to reduce the memory capacity of the microprogram memory.

REFERENCES:
patent: 3949370 (1976-04-01), Reyling, Jr.
patent: 3980992 (1976-09-01), Levy
patent: 4008462 (1977-02-01), Kanda
patent: 4021781 (1977-05-01), Candel
patent: 4091446 (1978-05-01), Demonte
patent: 4099230 (1978-07-01), Mead
patent: 4224668 (1980-09-01), Peters
patent: 4323964 (1982-04-01), Gruner

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