Method of making a stacked capacitor DRAM cell

Details Method of making a stacked capacitor DRAM cell Method of making a stacked capacitor DRAM cell

1990-04-30

1991-04-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 60, 437195, 437919, 357 236, H01L 2170

Patent

active

050064819

ABSTRACT:
A capacitor is formed for use with a DRAM storage cell by lying down alternating layers of polycrystalline silicon for the storage node and the ground plate. A buried bit line allows the capacitor area to cover a significant fraction of the cell layout area. The alternating storage node and ground plates of the capacitor are laid down alternately, and connected together as they are formed. The number of interleaved layers which can be used to form the capacitor can easily be varied to suit process requirements.

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Koyanagi et al., "Novel High Density Stacked Capacitor MOS RAM", Japanese J. of App. Physics, vol. 18 (1979), Supplement 184, pp. 35-42.

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