Phase and frequency adjustable digital phase lock logic system

Details Phase and frequency adjustable digital phase lock logic system Phase and frequency adjustable digital phase lock logic system

1991-12-30

1993-09-14

Kuntz, Curtis

Pulse or digital communications

Spread spectrum

Direct sequence

328 72, 307511, H03D 324

Patent

active

052456374

ABSTRACT:
A phase lock logic system is provided for (i) determining differences in phase and frequency of a received composite clock and data signal with respect to a local clock signal and (ii) providing control signals to enable accurate sampling and reconstruction of the received data. The system includes a delay element which outputs a plurality of phase-delayed signals each being incrementally shifted in phase from the local clock signal. A sorting circuit receives the phase-delayed local clock signals and the incoming composite signal, defines a number of time intervals in each cycle of the local clock signal equal to the number of phase-delayed local clock signals, and sorts positive and negative going transitions in the received composite signal into the defined time intervals. Counters indicate the number of transitions occurring during a selected time interval. A logic circuit reads the counters, determines the differences in frequency and phase of the received composite signal with respect to the local clock signal, and outputs first and second control signals. A barrel shifter responsive to the first control signal selects which of the counters counts the number of transitions occurring in a given time interval. A multiplexer responsive to the first and second control signals extracts the phase-delayed local clock signal which most closely approximates the phase and frequency of the received composite signal. A regenerator compares the extracted signal to the received composite signal and outputs regenerated data.

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