Compounding preprocessor for cache for identifying multiple inst

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395375, 364230, 364260, 3642631, 364DIG1, G06F 938, G06F 1300

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active

054653770

ABSTRACT:
A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the compounding information for the instructions is examined and those instructions indicated for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.

REFERENCES:
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patent: 4476525 (1984-10-01), Ishii
patent: 4928226 (1990-05-01), Kamada et al.
patent: 5027270 (1991-06-01), Riordan et al.
patent: 5075844 (1991-12-01), Jardine et al.

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