Interface unit facilitating communication between data processor

Details Interface unit facilitating communication between data processor Interface unit facilitating communication between data processor

1978-06-06

1980-10-21

Shaw, Gareth D.

Boots, shoes, and leggings

235 92CT, G06F 300

Patent

active

042297885

ABSTRACT:
A peripheral unit such as a teletypewriter, associated with a data processor but operating at a relatively slow rate so as to require an interruption of the processor's program when transmitting data, communicates with the processor through an interface unit comprising a sequential network switchable from a quiescent state (D) to an active state (C) via a preparatory state (A) and an intermediate state (B). The sequential network assumes its preparatory state (A) upon the appearance, at the interface unit, of an input/output instruction read out from a program store in the processor and addressed to the associated peripheral unit; the changeover to the intermediate state (B) occurs immediately thereafter if that peripheral unit emits a "data ready" signal (s). In the absence of overriding priorities within the processor or from higher-ranking peripheral units, an authorization signal (p) from the processor results in a switchover to the active state (C) commanding a program interruption; a confirmation signal (k) from the processor then restores the quiescent state (D) after causing transmission of the address of the associated peripheral unit to the processor, along with the data available at that unit.

REFERENCES:
patent: 3902162 (1975-08-01), Parkinson
patent: 3944980 (1976-03-01), Riedmayr
patent: 4004283 (1977-01-01), Bennett
patent: 4102492 (1976-07-01), Gold

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