Process for fabricating a semiconductor device

Details Process for fabricating a semiconductor device Process for fabricating a semiconductor device

1992-10-07

1993-09-14

Thomas, Tom

Fishing, trapping, and vermin destroying

437 40, 437 44, H01L 2170

Patent

active

052448231

ABSTRACT:
A process for fabricating a semiconductor device having a non-uniformly and lightly doped channel comprising the steps of forming on a Si substrate an isolation region of a field oxide and an active region of a thin SiO.sub.2 layer; performing first channel doping by implanting first conductivity type ions; after removing said thin SiO.sub.2 layer, forming a gate oxide dielectric and a gate electrode thereon; performing a second channel doping by implanting said type ions; depositing a thin polysilicon layer; depositing a SiO.sub.2 layer on said thin polysilicon layer; etching to remove a portion of said SiO.sub.2 layer and thin polysilicon layer to form a side wall; and implanting second conductivity type ions followed by heat treatment to provide source and drain regions.

REFERENCES:
patent: 3867197 (1975-02-01), Richman
patent: 3895966 (1975-07-01), MacDougall et al.
patent: 3912545 (1975-10-01), Armstrong
patent: 4033797 (1977-07-01), Dill et al.
patent: 4052229 (1977-10-01), Pashley
patent: 4173818 (1979-11-01), Bassous et al.
patent: 4356623 (1982-11-01), Hunter
patent: 4369072 (1983-01-01), Bakeman, Jr. et al.
patent: 4597824 (1986-07-01), Shinada et al.
patent: 4729001 (1988-03-01), Haskell
patent: 4735914 (1988-04-01), Hendrickson
patent: 4808544 (1989-02-01), Matsui
patent: 4845047 (1989-07-01), Holloway et al.
patent: 4994404 (1991-02-01), Sheng et al.
patent: 5015595 (1991-05-01), Wollesen
patent: 5015598 (1991-05-01), Verhaar
International Electron Devices Meeting 1985 Washington, D.C. Dec. 1-4, 1985 pp. 230-233; Christopher F. Codella et al.: "Halo Doping Effects in Submicron DI-ODD Device Design".
IEEE Electron Device Letters, vol. 11, No. 6, Jun. 1990, New York pp. 253-255; James R. Pfiester et al.: "A Selective Deposited Poly-Gate ITLDD Process with Self-Aligned LDD/Channel Implantation".
IBM Technical Disclosure Bulletin, vol. 22, No. 6, Nov. 1979, New York R. C. Varshney "Double Polysilicon Depletion-Model MOS Transistor Structure".

Affiliated with

Also associated with

Rating

Process for fabricating a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for fabricating a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating a semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2026118