Boots – shoes – and leggings
Patent
1993-08-05
1996-04-02
Bowler, Alyssa H.
Boots, shoes, and leggings
364754, 364759, 364760, 364DIG2, 364258, 3642581, 3642582, G06F 752
Patent
active
055049150
ABSTRACT:
A carry-save adder for use in a binary multiplier with a reduced number of full adder stages. The carry-save adder is for summing columns of binary data and is implemented with a plurality of one-bit and two-bit full adders. The one-bit and two-bit full adders are configured in a plurality of interconnected modified Wallace-Tree adders, each modified Wallace-Tree adder for summing binary data bits from one or more columns and generating a partial sum and a partial carry. Each modified Wallace-Tree adder has a plurality of stages comprising a combination of one-bit and two-bit full adders for reducing the number of the binary data bits, the last stage comprising a single one-bit full adder for generating the partial sum and partial carry results. A plurality of conductors interconnects the stages of each modified Wallace-Tree adder with stages in the same modified Wallace-Tree adder and with stages in other modified Wallace-Tree adders.
REFERENCES:
patent: 4660165 (1987-04-01), Masumoto
patent: 4839848 (1989-06-01), Peterson et al.
patent: 4897809 (1990-01-01), Shahriary et al.
patent: 4901270 (1990-02-01), Galbi et al.
patent: 4910508 (1990-03-01), Yamazaki
patent: 5036483 (1991-07-01), Virtue
patent: 5265043 (1993-11-01), Naini et al.
patent: 5347482 (1994-09-01), Williams
Goto et al, ("A 54.times.54-b Regularly Structured Tree Multiplier") Sep. 1992; IEEE, pp. 1229-1235.
Nagamatsu et al. (A 15-ns 32.times.32-b CMOS Multiplier with an Improved Parallel Structure Apr. 1990.
Mori et al. "A 10-ns 54.times.54 b parallel Structured Full Array Multiplier with 0.5 .mu.m CMOS" Apr. 1991.
Wang et al "An Architecture for Parallel Multipliers" IEEE 1990, pp. 403-407.
Montoye et al. "An 18ns 56-bit Multiplier-Adder Circuit" pp. 46-47, 262.
Pang, K. F., Architectures for Pipelined Wallace Tree Multiplier-Accumulators. IEEE pp. 247-250 (1990).
Brent et al., "A Regular Layout for Parallel Adders," IEEE Transactions on Computers, C-31(3):260-264, Mar. 1982.
Takagi et al., "High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree," IEEE Transactions on Computers, C-34 (9):789-796, Sep. 1985.
"Computer Arithmetic," pp. A-1 through A-66.
Bowler Alyssa H.
Donaghue L.
Hyundai Electronics America
LandOfFree
Modified Wallace-Tree adder for high-speed binary multiplier, st does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Modified Wallace-Tree adder for high-speed binary multiplier, st, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Modified Wallace-Tree adder for high-speed binary multiplier, st will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2024386