Firmware selectable address location and size for cis byte and a

Details Firmware selectable address location and size for cis byte and a Firmware selectable address location and size for cis byte and a

1995-06-22

1996-11-05

An, Meng-Ai T.

Boots, shoes, and leggings

395828, 395830, 395834, 395882, 39549703, 3642452, 36492792, 36492798, 36492799, 3649585, 364959, 3649582, 364961, 364DIG2, G06F 1300, G06F 1202

Patent

active

055726836

ABSTRACT:
An interface card has an interface logic block for interfacing a peripheral device with a computer host and for selecting either a common memory mode or an audio mode where the computer host can enable or disable a common memory read or write operation in the common memory mode. In the common memory mode, the computer host can choose to read card information service (CIS) bytes internally or externally. The interface logic block has, (a) a first external pin used either for a common memory chip select (CMCS) signal in the common memory mode or for an audio-in (AudIn) signal for the audio mode, (b) a second external pin used either for a common memory write (CMWR) signal in the common memory mode or for an audio-out (AudOut) signal in the audio mode, (c) a plurality of registers, (d) a logic circuit coupled to the registers, and (e) a microcontroller which can enable or disable the common memory write operation. The registers further include a configuration option register (COR), a card configuration and status register (CCSR), a pin replacement register organization (PRRO), a memory card address register, a memory card data register and an interface configuration register (ICR). Attribute memory range select bits in the ICR allow firmware selectable attribute memory locations of CIS bytes, the COR, CCSR and PRRO.

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PCMCIA PC card standard release 2.01.

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