Stack memory system including an address buffer for generating a

Details Stack memory system including an address buffer for generating a Stack memory system including an address buffer for generating a

1990-11-28

1993-12-07

Dixon, Joseph L.

Boots, shoes, and leggings

395400, 364DIG1, 3642605, 3642545, G06F 1202

Patent

active

052690121

ABSTRACT:
A stack memory includes an address input section, a memory element array, a stack pointer, and an address buffer. The address input section has "n" bits where "n" denotes a predetermined number. The memory element array has 2.sup.n words and is connected to the address input section. The stack pointer generates a first address signal having "n" bits, and an n-th bit of the first address signal is inverted by a control signal. The address buffer is connected between the stack pointer and the address input section. The address buffer generates a second address signal from the first address signal and outputs the second address signal to the address input section. The second address signal remains equal to the first address signal in bits except an n-th bit, and the n-th bit of the first address signal is inverted again by the control signal to be converted into the n-th bit of the second address signal.

REFERENCES:
patent: 4905201 (1990-02-01), Ohira et al.
patent: 5023828 (1991-06-01), Grundmann et al.

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