Processor with a respective latch provided for each pipelined st

Details Processor with a respective latch provided for each pipelined st Processor with a respective latch provided for each pipelined st

1993-09-16

1995-11-07

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 364DIG2, 3642318, G06F 938

Patent

active

054653347

ABSTRACT:
A processor which executes instructions using pipeline processing having an effective address calculation stage and an operation stage, at least one stage existing between the effective address calculation stage and the operation stage. A register temporarily stores data. A pipeline latch part includes a respective latch provided for, and respectfully corresponding to, each stage between the effective address calculation stage and the operation stage and includes a respective latch corresponding to the operation stage. During the effective address calculation stage, the pipeline latch part receives data stored in the register and transfers the received data through the each respective latch in accordance with the execution of instructions to provide the data to the respective latch corresponding to the operation stage when the operation stage performs an operation. During the effective address calculation stage, an effective address calculation part receives data stored in the register and adds the data to a displacement of an instruction code, to thereby calculate an effective address. During the operation stage, an operation part receives data stored in the register, receives data from the latch corresponding to the operation stage in the pipeline latch part, and executes an operation on the received data.

REFERENCES:
patent: 5185868 (1993-02-01), Tran

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