Data processor with means for separately receiving and processin

Details Data processor with means for separately receiving and processin Data processor with means for separately receiving and processin

1994-06-10

1995-11-28

Ray, Gopal C.

Boots, shoes, and leggings

3642302, 3642412, 3642624, 3642597, 364DIG1, 395734, 395735, 395736, 395740, G06F 1324, G06F 946

Patent

active

054716209

ABSTRACT:
A data processor which is provided with a flag in a Processor Status Word (PSW) 116 for storing prohibiting/enabling status for receiving all of the interrupt requests, and in which the instruction execution control unit 114 controls so that the flag becomes in the enabling status when an interrupt request having a priority level is received and the flag becomes in the prohibiting status when an interrupt request having no priority level is received. Hence, for interrupt requests having priority levels, an interrupt request of high priority level can be received immediately without via the interrupt prohibiting status. For interrupt requests having priority levels, it becomes possible to receive an interrupt request of higher priority level without via the interrupt prohibiting status. For interrupt requests having no priority level such as for debugger and the like, it becomes unnecessary to perform a multi-interrupt processing.

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Single-Chip 16-Bit CMOS Microcomputer, 1989 Mitsubishi Semiconductor Data Book Mitsubishi Electric Corporation, May 1989, pp. 2-15.

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