Method and apparatus for negating an operand

Details Method and apparatus for negating an operand Method and apparatus for negating an operand

1991-08-30

1993-12-07

Nguyen, Long T.

Boots, shoes, and leggings

G06F 752

Patent

active

052688585

ABSTRACT:
A multiplier system 12 is disclosed which provides for the negation of an operand stored in an operand register 14. When a negative operand must be loaded into a partial product generator 26, a carry bit is selectively generated in carry logic 44 and a selected bit or bits within the partial product is set to zero. During a subsequent pass through the multiplier system 12, a bit is added at a block 46 to provide for the addition of the required quantity for the negation of the operand.

REFERENCES:
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patent: 4597053 (1986-06-01), Chamberlin
patent: 4631696 (1986-12-01), Sakamoto
patent: 4709226 (1987-11-01), Christopher
patent: 4719590 (1988-01-01), Aman
patent: 4748584 (1988-05-01), Noda
patent: 4866656 (1989-09-01), Hwang
patent: 4918640 (1990-04-01), Heimsch et al.
patent: 4935890 (1990-06-01), Funyu

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