Boots – shoes – and leggings
Patent
1994-06-21
1995-11-28
Ray, Gopal C.
Boots, shoes, and leggings
364DIG1, 364229, 3642292, 3642301, 3642319, 36423223, 3642327, 364240, 3642407, 364241B, 3642426, 3642428, 364243, 3642433, 39520008, 395477, 395312, G06F 1300
Patent
active
054715920
ABSTRACT:
There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories, are contained on a single silicon chip.
REFERENCES:
patent: 3581286 (1971-05-01), Beausoleil
patent: 3651473 (1972-03-01), Faber
patent: 3787818 (1974-01-01), Arnold et al.
patent: 4058316 (1977-11-01), Miller
patent: 4195344 (1980-03-01), Yamataki
patent: 4412286 (1983-10-01), O'Dowd et al.
patent: 4442503 (1984-04-01), Schutt et al.
patent: 4562535 (1985-12-01), Vincent et al.
patent: 4633245 (1986-12-01), Blout et al.
patent: 4644496 (1987-02-01), Andrews
patent: 4731724 (1988-03-01), Michel et al.
patent: 4747043 (1988-05-01), Rodman
patent: 4779210 (1988-09-01), Katsura
patent: 4794517 (1988-12-01), Jones et al.
patent: 4807184 (1989-02-01), Shelor
patent: 4811210 (1989-03-01), McAulay et al.
patent: 4834483 (1989-05-01), Arthurs et al.
patent: 4852083 (1989-07-01), Niehaus et al.
patent: 4891787 (1990-01-01), Gifford et al.
patent: 4901360 (1990-02-01), Shu et al.
patent: 4905141 (1990-02-01), Brenza
patent: 4949243 (1990-08-01), Ali
patent: 4949280 (1990-08-01), Littlefield
patent: 4973956 (1990-11-01), Lin et al.
patent: 4985830 (1991-01-01), Atac et al.
patent: 4989131 (1991-01-01), Stone
patent: 4991084 (1991-02-01), Rodiger et al.
patent: 5032985 (1991-07-01), Cunnan
patent: 5041971 (1991-08-01), Canvey et al.
patent: 5081575 (1992-01-01), Hillis
patent: 5093826 (1992-03-01), Leichum
patent: 5247689 (1993-09-01), Eulert
"Interconnecting Off-the-Shelf Microprocessors", Humond Al-Sadoun et al, AFIPS Conference Proceedings, 1985 National Computer Conference, Jul. 15-18, 1985, Chicago, Illinois.
A. M. Despain, et al., "High Performance Prolog, The Multiplicative Effect of Several Levels of Implementation", IEEE, pp. 178-184, 1986.
TMS34010 User's Guide, Texas Instruments, 1988, pp. i-x, 1-1--1-11.
"The Connection Machine", by W. D. Hillis, published in The MIT Press (1985).
"Handling Real Time Images Comes Naturally to Systolic Array Chip", by Hannaway, Shea, Bishop, in Electronic Design, pp. 289-300 (1984).
"Systolic Array Chip Recognizes Visual Patterns Quicker Than a Wink", by W. W. Smith, P. Sullivan, in Electronic Design, pp. 257-266 (1984).
"Real Time 3D Object Tracking in a Rapid Prototyping Environment", by Robert J. Gove, in Electronic Imaging '88 (1988).
"Integration of Symbolic and Multiple Digital Signal Processors with the Explorer/Odyssey for Image Processing and Understanding Applications", by Robert J. Gove, in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 968-971 (May, 1987).
"The Use of Parallel-Processing Computers in Digital Image Processing", by Lew Brown, published by Alliant Computer Systems Corp., Littleton, Mass.
"VITec Parallel C Compiler", by T. Butler, published by Visual Information Technologies, Inc., Plano, Tex., pp. 741-747.
"A Single Board Image Computer with 64 Parallel Processors", by Stephen Wilson, published in Electronic Imaging '87, International Electronic Imaging Exposition & Conference (1987), pp. 470-475.
"The Androx Parallel Image Array Processor", by Wayne Threatt, in Electronic Imaging '87, International Electronic Imaging Exposition & Conference (1987), pp. 1061-1064.
"Design of a Massively Parallel Processor", by Kenneth Batcher, IEEE Transactions on Computers, V. C-29, No. 9 (1980).
"High Resolution Frame Grabbing and Processing Through Parallel Architecture", by Daniel Crevier, published by Coreco, Inc., Quebec, Canada.
"Multiple Digital Signal Processor Environment for Intelligent Signal Processing" by Gass, et al., in Proceedings of the IEEE, V. 75, No. 9 (Sep. 1987) pp. 1246-1259.
"Architecture and Design of the MARS Hardware Accelerator", Agrawall, et al. in 24th ACM/IEEE Design Automation Conference (1987), pp. 101-107.
"Digital Video & Image Processors", by O'Brien, Mather & Holland, published by Plessey Semiconductors (1989).
"An Architectural Study, Design and Implementation of Digital Image Acquisition, Processing and Display Systems with Micro-Processor-Based Personal Computers and Charge-Coupled Device Imaging Technology", a dissertation by Robert J. Gove, SMU (1986).
"A Medium Grained Parallel Computer for Image Processing", by R. S. Cok, published by Digital Technology Center, Eastman Kodak Co., Rochester, N.Y.
Balmer Keith
Gove Robert J.
Guttag Karl M.
Ing-Simmons Nicholas K.
Donaldson Richard L.
Kesterson James C.
Marshall, Jr. Robert D.
Ray Gopal C.
Sheikh Ayaz R.
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