Semiconductor memory device including a clocking circuit for con

Details Semiconductor memory device including a clocking circuit for con Semiconductor memory device including a clocking circuit for con

1999-07-01

2000-10-03

Hoang, Huan

Static information storage and retrieval

Addressing

Sync/clocking

365194, 365236, G11C 800

Patent

active

061282480

ABSTRACT:
A semiconductor memory device is provided which includes a memory cell array, a read circuit which reads data from said memory cell array, and an external terminal which receives an external clock signal. A first input circuit receives the external clock signal and outputs a first internal clock signal delayed from the external clock signal. A second input circuit receives the first internal clock signal and outputs a second internal clock signal delayed from the first internal clock signal. The memory device also includes a circuit which counts a clock signal having a frequency higher than that of the external clock signal and a circuit which starts the counting in response to the second internal clock signal, reverses the direction of said counting in response to the first internal clock signal and detects when a count of said counting circuit again reaches the count at the start of said counting, thereby outputting a timing signal therefrom. A clock output circuit is provided which outputs a third internal clock signal for controlling the operation of said read circuit based on the timing signal.

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T. Saeki et al., "SP 23.4: A 2.5 ns Clock Access 250 MHz 256Mb SDRAM with a Synchronous Mirror Delay", 1996 IEEE Int'l Solid-State Circuits Conference, Session 23/DRAM/Paper SP23.4.

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