Semiconductor memory with PN junction potential reduction in a w

Details Semiconductor memory with PN junction potential reduction in a w Semiconductor memory with PN junction potential reduction in a w

1999-03-29

2000-10-03

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518504, G11C 1134

Patent

active

061282308

ABSTRACT:
A semiconductor memory device includes a plurality of memory cells, a row sub-decoder, a row main decoder and reducing means. The memory cells are arranged in a matrix form. The row sub-decoder selects each row of the memory cells. The row main decoder decodes a row address signal and supplies a control signal into the row sub-decoder. The row main decoder is structured by at least one transistor having a PN junction breakdown voltage. The reducing means reduces the PN junction breakdown voltage during a writing mode.

REFERENCES:
patent: 4769787 (1988-09-01), Furusawa et al.
patent: 5253200 (1993-10-01), Arakawa
patent: 5680349 (1997-10-01), Atsumi et al.
Umezawa, et al., A 5-V-Only Operation 0.6-.mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure, 11/92, vol. 27, No. 11, pp. 1540-1545.

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