Method and circuit for reading low-supply-voltage nonvolatile me

Details Method and circuit for reading low-supply-voltage nonvolatile me Method and circuit for reading low-supply-voltage nonvolatile me

1997-06-18

2000-10-03

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518521, G11C 1602

Patent

active

061282251

ABSTRACT:
The read circuit has an array branch connected to an array cell, and a reference branch connected to a reference cell; the array branch presents an array load transistor interposed between a supply line and the array cell, and the reference branch presents a reference load transistor interposed between the supply line and the reference cell; and the array and reference load transistors form a current mirror wherein the array load transistor is diode-connected and presents a first predetermined channel width/length ratio, and the reference load transistor presents a second predetermined channel width/length ratio N times greater than the first ratio, so that the current flowing in the array cell is supplied, amplified, to the reference branch.

REFERENCES:
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patent: 5396467 (1995-03-01), Liu et al.
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patent: 5487045 (1996-01-01), Trodden
patent: 5627790 (1997-05-01), Golla et al.
patent: 5717640 (1998-02-01), Hashimoto
Ashmore et al., "A 20ns 1Mb CMOS BurstMode EPROM," in 1989 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, New York, New York., pp. 40-41.

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