Method and apparatus for latching data around a logical data pro

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307452, 307481, H03K 19017

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active

052685969

ABSTRACT:
A control method for a data processing circuit which controls the timing of two clocks which independently control data latch circuits connected respectively with an input side and an output side of a logic circuit. The two clocks are held at a level which allows both data latch circuits to sample an input signal for a predetermined period. A data latch circuit comprises a first gate controlling whether or not an input signal is conducted to the logic circuit, an input end of a buffer circuit for latching the data signal and an output end of a second gate which causes an output of the buffer circuit to pass to an output end of the first gate, and a data processing circuit capable of sampling data, logically processing it, latching the result of the processing, and outputting it in one clock cycle, by interposing a logic circuit between the aforementioned two data latch circuits.

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