Method and apparatus for sequencing addresses of a fast Fourier

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364200, G06F 1534

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active

043934579

ABSTRACT:
An apparatus and method for generating a specific sequence of addresses of values of an array stored in a digital memory. The addresses are generated by a first counter which generates a seed value and a second counter which generates a control value, the control value controlling a bit inserter and a programmable shifter to set, respectively, the bit place position of bit insertion and the amount of shift. The output of the bit inserter is the row position of related addresses for butterfly operation of a fast Fourier transform array. The output of the shifter is the address of coefficients associated with the complex rotation of the butterfly operation. The apparatus is an integrated circuit intended for use as a modular integrated circuit in connection with digital memory means and central processing means including a digital multiplying means.

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patent: 4138730 (1979-02-01), Ali
Moyer, "A High-Speed Indexing Unit for FFT Algorithm Implementation", Computer Design, Dec., 1971, pp. 45-48.

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