Registered RAM array with parallel and serial interface

Details Registered RAM array with parallel and serial interface Registered RAM array with parallel and serial interface

Filed on

1989-02-28

Date issued

1992-03-24

Examiner

Chan, Eddie P.

Patent Class

Excavating

Other Related Categories

395425, 371 211, G06F 1100, G11C 2900

Type

Patent

Status

active

Patent number

050994816

Description

ABSTRACT:
A serial protocol register and an initialization counter are configured to initialize (program) a RAM array. The register is configured to receive, in serial format, an initial address to be loaded into the counter. Also, the register is configured to receive, in serial format, a series of machine states (data words), each to be stored in the RAM array. In addition, the register is configured to clock the counter following each received machine state. The counter is configured to develop a series of addresses, each for accessing the RAM array to store in the array a corresponding one of the machine states.

REFERENCES:
patent: Re29642 (1978-05-01), Kwiatkowski et al.
patent: 4159535 (1979-06-01), Fuhrman
patent: 4194243 (1980-03-01), Tsuda
patent: 4476560 (1984-10-01), Miller et al.
patent: 4538241 (1985-08-01), Levin et al.
patent: 4710927 (1987-12-01), Miller
patent: 4935929 (1990-06-01), Sidman et al.
Advanced Micro Devices, Inc., "Am9151 1024.times.4 Registered Static RAM with SSR.TM.--On-Chip Diagnostics Capability", Publ. No. 05385, May 1986, pp. 4-238-4-250.

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