Excavating
Patent
1989-02-08
1991-03-19
Atkinson, Charles E.
Excavating
371 224, G01R 3128
Patent
active
050017136
ABSTRACT:
A boundary test architecture for use in an integrated circuit (10) comprises input and output test registers (12, 22) having functions controlled by an event qualifying module (EQM) (30). The EQM (30) receives a signal from the output test register (22) indicating that a matching condition has been met. In response to a matching condition, EQM (30) may control the input and output test registers (12, 22) to perform a variety of tests on the incoming and outgoing data. During testing, the internal logic (20) may continue to operate at-speed, thereby allowing the test circuitry to detect faults which would not otherwise be discoverable. A memory buffer (64) may be included to store a plurality of input data for test data.
REFERENCES:
patent: 4598401 (1986-07-01), Whelan
patent: 4635261 (1987-01-01), Anderson et al.
patent: 4801870 (1989-01-01), Eichelbarger et al.
patent: 4857835 (1989-08-01), Whetsel, Jr.
patent: 4860288 (1989-08-01), Teske et al.
patent: 4872169 (1989-10-01), Whetsel, Jr.
patent: 4875003 (1989-10-01), Burke
patent: 4893072 (1990-01-01), Matsumoto
Sellers et al., Error Detecting Logic for Digital Computers, McGraw-Hill Co., 1968, pp. 207-211.
Atkinson Charles E.
Barndt B. Peter
Comfort James T.
Sharp Melvin
Texas Instruments Incorporated
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