Patent
1990-06-26
1991-03-19
Tarcza, Thomas H.
357 45, H01L 2704, H01L 27082, H01L 27102
Patent
active
050014870
ABSTRACT:
A semiconductor integrated circuit device is disclosed. The circuit device uses modified (m+n) input cells, each equipped with high load driving functional elements disposed at the periphery of the cell, and having n signal input terminal(s) in addition to m normal signal input terminals that are incorporated in the cell.
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patent: 4414547 (1983-11-01), Knapp et al.
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patent: 4556947 (1985-12-01), Prioste et al.
patent: 4593205 (1986-06-01), Bass et al.
patent: 4617479 (1986-10-01), Hartmann et al.
Lopez et al., "A Dense Gate Matrix Layout Method for MOS VLSI", IEEE Journal of Solid State Circuits, vol. SC-15, No. 4, Aug. 1980, pp. 736-740.
Electronics and Communications in Japan, vol. 66, No. 1, Jan. 1983, pp. 111-119.
Mamyoda Haruo
Matsubara Toshiaki
Suzuki Yasunaga
Uragami Akira
Hitachi , Ltd.
Sotomayor John B.
Tarcza Thomas H.
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