Low noise output buffer circuit

Details Low noise output buffer circuit Low noise output buffer circuit

1990-07-02

1991-03-19

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307263, 307592, 3072721, 3072722, H03K 1902, H03K 512, H03K 3289

Patent

active

050013696

ABSTRACT:
A low-noise output buffer circuit that activates and deactivates the output by means of a two stage NAND and FET circuit, which senses a low voltage in a first stage pull-up (pull-down) NAND output before activating pull-down (pull-up) devices and the second stage, thereby minimizing the power supply current spike that normally appears during input and output switching operations.

REFERENCES:
patent: 4695743 (1987-09-01), Des Brisay, Jr.
patent: 4820942 (1989-04-01), Chan
patent: 4825101 (1989-04-01), Walters, Jr.
patent: 4827157 (1989-05-01), Machida et al.
patent: 4918332 (1990-04-01), Nix

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