Floating guard region and process of manufacture for semiconduct

Details Floating guard region and process of manufacture for semiconduct Floating guard region and process of manufacture for semiconduct

1980-11-17

1983-11-08

Clawson, Jr., Joseph E.

357 23, 357 41, 357 52, 357 53, 357 86, H01L 29747

Patent

active

044145608

ABSTRACT:
A high-voltage, high current switching device is formed of two D-MOS transistors which are merged together to have a common drain and insulated metal gate. At the time P-type regions for the two D-MOS transistors are formed, a floating P-type region is formed between them. A field plate is used in combination with the floating guard region.

REFERENCES:
patent: 4199774 (1980-04-01), Plummer
patent: 4286279 (1981-08-01), Hutson
patent: 4331884 (1982-05-01), Svedberg
A. Lebedev, "Analysis of Process in Multilayer Semiconductor Structures of the N-P-N-P-N-P Type", Physics of P-N JCNS. and Semiconductor Devices, 2nd Ed., London, 1976, pp. 321-329.

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