Three input arithmetic logic unit forming the sum of a first Boo

Details Three input arithmetic logic unit forming the sum of a first Boo Three input arithmetic logic unit forming the sum of a first Boo

1993-11-30

1995-11-07

Malzahn, David H.

Boots, shoes, and leggings

364768, G06F 738

Patent

active

054652243

ABSTRACT:
A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The arithmetic logic unit (230) first forms a Boolean combination and then forms an arithmetic combination. The current instruction drives an instruction decoder (250, 245) that generates the functions signals F0-F7 which control the combination formed. The arithmetic logic unit (230) includes a first three input Boolean function generator (496) forming a Boolean combination F1(A,B,C), a second three input Boolean function generator (497) forming a Boolean combination F2(A,B,C), and an adder (495) forming the sum of the two Boolean combinations. The first Boolean combination F1(A,B,C) and the second Boolean combination F2(A,B,C) are independently selected from the set of all possible Boolean combinations of three multibit input signals A, B and C. The adder (495) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit. This carry input is determined by the combination being formed, and generally is "1" only during subtraction.

REFERENCES:
patent: 3783254 (1974-01-01), Eichelberger
patent: 4263660 (1981-04-01), Prioste
patent: 4399516 (1983-08-01), Blahut et al.
patent: 4467409 (1984-08-01), Potash et al.
patent: 4785393 (1988-11-01), Chu et al.
patent: 5299319 (1994-03-01), Vassiliadis et al.

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