Process for fabricating III-V devices using a composite dielectr

Details Process for fabricating III-V devices using a composite dielectr Process for fabricating III-V devices using a composite dielectr

1989-04-19

1991-03-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437184, 437 41, 437176, 437912, 437 56, 437978, 437 39, 148DIG43, 148DIG20, H01L 21314, H01L 21338

Patent

active

050010760

ABSTRACT:
A III-V semiconductor surface (10') of a III-V substrate (10) is provided with a thick dielectric layer (40), preferably comprising a composite nitride/oxide layer (40a/40b). A layer of comparatively thin silicon nitride layer (40a) is formed on the substrate and a comparatively thicker silicon dioxide layer (40b) is formed thereover. The composite dielectric layer acts as a good ion absorber during ion implantation (54), thereby masking the substrate from ions in undersirable locations. Further, the composite dielectric layer provides appropriate contrast for alignment marks, thereby reducing the number of masking steps and the amount of gate area in FETs otherwise required to compensate for potential misalignment. The composite dielectric layer affords surface protection, which not only keeps the semiconductor clean during processing, but also provides a cap during annealing. Finally, the composite dielectric layer separates gate metal interconnects from the substrate surface, thereby reducing capacitance and undesirable substrate biasing.

REFERENCES:
patent: 3861969 (1975-01-01), Ono et al.
patent: 4396437 (1983-08-01), Kwok et al.
patent: 4855246 (1989-08-01), Codella et al.
Ghandhi, S. K., VLSI Fabrication Principles, John Wiley & Sons, 1983, pp. 418-431, 598-605.

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