Active solid-state devices (e.g. – transistors – solid-state diode – Bulk effect device – Bulk effect switching in amorphous material
Patent
1999-05-11
2000-08-15
Guay, John
Active solid-state devices (e.g., transistors, solid-state diode
Bulk effect device
Bulk effect switching in amorphous material
257 5, 257774, H01L 4500
Patent
active
06104038&
ABSTRACT:
A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared. The pores thus defined are further equally spaced from adjacent pores by a spacing ranging from approximately 0.25 to 0.5 microns. The pores thus defined may then be used to fabricate an array of chalcogenide memory cells.
REFERENCES:
patent: 3423646 (1969-01-01), Cubert et al.
patent: 3796926 (1974-03-01), Cole et al.
patent: 4099260 (1978-07-01), Lynes et al.
patent: 4115872 (1978-09-01), Bluhm
patent: 4174521 (1979-11-01), Neale
patent: 4194283 (1980-03-01), Hoffmann
patent: 4203123 (1980-05-01), Shanks
patent: 4227297 (1980-10-01), Angerstein
patent: 4272562 (1981-06-01), Wood
patent: 4458260 (1984-07-01), McIntyre et al.
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4502208 (1985-03-01), McPherson
patent: 4502914 (1985-03-01), Trumpp et al.
patent: 4569698 (1986-02-01), Feist
patent: 4630355 (1986-12-01), Johnson
patent: 4642140 (1987-02-01), Noufi et al.
patent: 4666252 (1987-05-01), Yaniv et al.
patent: 4677742 (1987-07-01), Johnson
patent: 4757359 (1988-07-01), Chiao et al.
patent: 4795657 (1989-01-01), Formigoni et al.
patent: 4804490 (1989-02-01), Pryor et al.
patent: 4809044 (1989-02-01), Pryor et al.
patent: 4823181 (1989-04-01), Mohsen et al.
patent: 4876220 (1989-10-01), Mohsen et al.
patent: 4876668 (1989-10-01), Thakoor et al.
patent: 4881114 (1989-11-01), Mohsen et al.
patent: 4892840 (1990-01-01), Esquivel et al.
patent: 5144404 (1992-09-01), Iranmanesh et al.
patent: 5166096 (1992-11-01), Cote et al.
patent: 5166758 (1992-11-01), Ovshinsky et al.
patent: 5177567 (1993-01-01), Klersy et al.
patent: 5216282 (1993-06-01), Cote et al.
patent: 5293335 (1994-03-01), Pernisz et al.
patent: 5296716 (1994-03-01), Ovshinsky et al.
patent: 5310693 (1994-05-01), Hsue
patent: 5335219 (1994-08-01), Ovshinsky et al.
patent: 5341328 (1994-08-01), Ovshinsky et al.
patent: 5359205 (1994-10-01), Ovshinsky
patent: 5363329 (1994-11-01), Troyan
patent: 5414271 (1995-05-01), Ovshinsky et al.
patent: 5429988 (1995-07-01), Huang et al.
patent: 5510629 (1996-04-01), Karpovich et al.
patent: 5534711 (1996-07-01), Ovshinsky et al.
patent: 5534712 (1996-07-01), Ovshinsky et al.
patent: 5536947 (1996-07-01), Klersy et al.
patent: 5687112 (1997-11-01), Ovshinsky
patent: 5714768 (1998-02-01), Ovshinsky et al.
patent: 5714795 (1998-02-01), Ohmi et al.
patent: 5751012 (1998-05-01), Wolstenholme et al.
patent: 5789758 (1998-08-01), Reinberg
patent: 5812441 (1998-09-01), Manning
patent: 5814527 (1998-09-01), Wolstenholme et al.
patent: 5841150 (1998-11-01), Gonzalez et al.
Kim and Kim, "Effects of High-Current Pulses on Polycrystalline Silicon Diode with n-type Region Heavily Doped with Both Boron and Phosphorus," J. Appl. Phys., 53(7):5359-5360, 1982.
Neal and Aseltine, "The Application of Amorphous Materials to Computer Memories," IEEE, 20(2):195-205, 1973.
Pein and Plummer, "Performance of the 3-D Sidewall Flash EPROM Cell," IEEE, 11-14, 1993.
Post and Ashburn, "Investigation of Boron Diffusion of Polysilicon and its Application to the Design of p-n-p Polysilicon Emitter Bipolar Transistors with Shallow Emitter Junctions," IEEE, 38(11):2442-2451, 1991.
Post et al., "Polysilicon Emitters for Bipolar Transistors: A Review and Re-Evaluation of Theory and Experiment," IEEE, 39(7):1717-1731, 1992.
Post and Ashburn, "The Use of an Interface Anneal to Control the Base Current and Emitter Resistance of p-n-p Polysilicon Emitter Bipolar Transistors," IEEE, 13(8):408-410, 1992.
Rose et al., "Amorphous Silicon Analogue Memory Devices," J. Non-Crystalline Solids, 115:168-170, 1989.
Schaber, et al., "Laser Annealing Study of the Grain Size Effect in Polycrystalline Silicon Schottky Diodes," J. Appl. Phys., 53(12):8827-8834, 1982.
Yamamoto et al., "The I-V Characteristics of Polycrystalline Silicon Diodes and the Energy Distribution of Traps in Grain Boundaries," Electronics and Communications in Japan, Part 2, 75(7):51-58, 1992.
Yeh et al., "Investigation of Thermal Coefficient for Polycrystalline Silicon Thermal Sensor Diode," Jpn. J. Appl. Phys., 31(Part 1, No. 2A):151-155, 1992.
Oakley et al., "Pillars--The Way to two Micron Pitch Multilevel Metallisation," IEEE, 23-29, 1984.
Gonzalez Fernando N. M.
Turi Raymond A.
Guay John
Micro)n Technology, Inc.
LandOfFree
Method for fabricating an array of ultra-small pores for chalcog does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating an array of ultra-small pores for chalcog, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating an array of ultra-small pores for chalcog will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2009336