Method and apparatus for instruction parity error recovery

Details Method and apparatus for instruction parity error recovery Method and apparatus for instruction parity error recovery

1983-03-24

1985-08-27

Smith, Jerry

Excavating

371 5, 371 9, G06F 1116

Patent

active

045382654

ABSTRACT:
A method and apparatus for instruction parity error recovery in a programmable data processor wherein the instruction parity error is logged for future reference, the instruction causing the error is reloaded to memory and the program is restarted at the point of error. This method for "soft" recovery from an instruction parity error forces a No-Operation instruction onto the processor's instruction bus in place of the faulty instruction when a parity error is detected during instruction fetch, stores the address of the instruction having the parity error, and forces the next instruction to the processor from a parity error recovery routine. The parity error recovery routine logs the error, restores the instruction from local disk storage or from a remote host system in communication with the programmable data processor and forces the processor to resume fetching instructions at the address where the error occurred.

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patent: 4360917 (1982-11-01), Sindelar et al.
patent: 4443849 (1984-04-01), Ohwada

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