Method and apparatus for performing hashing operations using Gal

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364715, G06F 752

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active

045382409

ABSTRACT:
The invention comprises a method and apparatus for performing a hashing operation on an N bit number under control of a prespecified N bit hashing constant which comprises performing N/K finite field partial multiplications of the object to be hashed by the hashing constant, utilizing K logic and combinatorial circuits all of which operate in parallel to completely evaluate the number in N/K operations.
Another feature of the present invention is that the hashing constant loaded into the system may be changed at will with a resultant changing of the hashing characteristics to suit a particular class of objects to be hashed. This is done by a "select" operation. In the "select" operation, the hashing constant is sequentially loaded into said K logic and combinatorial circuits, each of which comprises a feedback shift register (FSR), said feedback shift registers being so configured that at the end of K operational sequences each of said feedback shift registers contains said hashing constant shifted and permuted in accordance with the particular feedback configuration of said register, a number of bits proportional to its location in the sequence of feedback shift registers, such that the hashing constant in the shift register FSR.sub.i will be shifted in a predetermined direction (i-1) N/K bit positions. Each of the operational sequences referred to above comprises a hashing sequence which includes N/K shifts of the feedback shift registers.

REFERENCES:
patent: 4037093 (1977-07-01), Gregg et al.
patent: 4251875 (1981-02-01), Marver et al.
patent: 4473887 (1984-09-01), Odaka
Laws, Jr. et al., "A Cellular-Array Multiplier for GF(2.sup.m)", IEEE Trans. on Computers, Dec. 1971, pp. 1573-1578.

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