Electric power conversion systems – Current conversion – With voltage multiplication means
Patent
1989-09-25
1991-01-01
Wong, Peter S.
Electric power conversion systems
Current conversion
With voltage multiplication means
363 59, 307110, H02M 318
Patent
active
049823175
ABSTRACT:
integrated voltage multiplier circuit for low supply voltage. In order to improve the signal-to-noise ratio in battery-operated switched capacitor filter circuits in hearing aids, the range of modulation can be increased by doubling the supply voltage. A circuit for voltage multiplication in CMOS technology generates a negative voltage for a given voltage. In order to be able to utilize both clock phases, a two-stage embodiment is selected, both of these working onto a smoothing capacitor. The voltage multiplier circuit is driven by a fourth inverter stage and with a level converter having a connected, third inverter stage.
REFERENCES:
patent: 3790812 (1974-02-01), Fry
patent: 3824447 (1974-07-01), Kuwabara
patent: 4061929 (1977-12-01), Asano
patent: 4106086 (1978-08-01), Holbrook et al.
patent: 4199806 (1980-04-01), Patterson
patent: 4271461 (1981-06-01), Hoffmann et al.
patent: 4302804 (1981-11-01), Bader
patent: 4321661 (1982-03-01), Sano
patent: 4344003 (1982-08-01), Harmon et al.
patent: 4460952 (1984-07-01), Risinger
patent: 4616303 (1986-10-01), Mauthe
patent: 4621315 (1986-11-01), Vaughn et al.
patent: 4663701 (1987-05-01), Stotts
patent: 4792886 (1988-12-01), Sahm
patent: 4839787 (1989-06-01), Kojima et al.
"A 1.5 V. Single-Supply One-Transistor CMOS EEPROM", by B. Gerber, IEEE Journal of Solid-State Circuits, vol. SC-16, No. 3, Jun. 1981, pp. 195-199.
"A Set of 4 IC's In CMOS Technology for a Programmable Hearing Aid", by F. Callias et al, IEEE 1988 Custom Integrated Circuits Conference, No. 5, pp. 2-5, May 1988.
"Inductance-Less Up dc-dc Convertor", by S. Singer, IEEE Journal of Solid-State Circuits, vol. SC-17, No. 4, Aug. 1982, pp. 778-781.
"On-Chip High-Voltage Generation In MNOS Integrated Circuits Using An Improved Voltage Multiplier Technique", by J. F. Dickson, IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, Jun. 1976, pp. 374-378.
Siemens Aktiengesellschaft
Sterrett Jeffrey
Wong Peter S.
LandOfFree
Integrated voltage multiplier circuit for low supply voltage does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated voltage multiplier circuit for low supply voltage, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated voltage multiplier circuit for low supply voltage will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2001084