Highly scalable dynamic RAM cell with self-signal amplification

Details Highly scalable dynamic RAM cell with self-signal amplification Highly scalable dynamic RAM cell with self-signal amplification

1983-09-30

1986-09-16

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

365182, 357 236, 358213, G11C 1134

Patent

active

046126295

ABSTRACT:
A dynamic RAM memory cell comprises an MOS read transistor whose conductivity state is determined by the state of charge on a first electrode overlying the read transistor channel region. The first electrode is connected through a buried contact opening to a diffused region in the substrate. This diffusion serves as a junction isolated storage node. This storage node can be charged or discharged through an MOS write transistor. The first electrode is capacitively coupled to a field plate held at a field potential. A control gate formed in a second electrode controls conduction through the write transistor and also allows selective reading in an array of read transistors. Nondestructive read can be achieved together with transistor amplification of the charge stored on the first electrode.
Reduction in memory array area is achieved by using the source diffusion of the read transistor also as a buried field plate and by using the drain diffusion of the read transistor of one memory cell also as the drain diffusion of the write transistor of an adjacent cell.

REFERENCES:
patent: 4344091 (1982-08-01), Gardner et al.
patent: 4441125 (1984-04-01), Parkinson
IEEE Trans. Ed., vol. 26, No. 6, Jun. 1979, Chatterjee et al., "A Survey of High Density Dynamic RAM Cell Concepts".
IEDM Abstracts 1980, (IEEE Publication), Terada et al., "A New Dynamic RAM Cell for VLSI Memories".

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