RISC processor having a cross-bar switch

Details RISC processor having a cross-bar switch RISC processor having a cross-bar switch

1991-08-28

1994-11-22

Bowler, Alyssa H.

Boots, shoes, and leggings

395375, 364DIG1, 364229, 3642292, 36423223, G06F 930

Patent

active

053676947

ABSTRACT:
An instruction cache unit output four instructions, each constituted by 32 bits, which are input to an instruction supplier. The instruction supplier distributes the four instructions to five. The five instructions are selectively supplied to two integer/logical arithmetic processor unit, two floating-point arithmetic processor unit, and a branch processor unit.

REFERENCES:
patent: 4766566 (1988-08-01), Chuong
patent: 4942525 (1990-07-01), Shintoui et al.
patent: 5197137 (1993-03-01), Kumar et al.
Glenn Hinton,"80960-Next Generation", IEEE Computer Society Press Washington D.C., 4189, pp. 13-17.

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