Parallel computer system including efficient arrangement for per

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3642401, 3642402, 364229, 3642295, 364230, 3642305, 36424294, 3642425, 3642687, 3642547, 364DIG1, 364DIG2, G06F 1206, G06F 1202, G06F 1314

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053676920

ABSTRACT:
A processing element array and a controller. The processing element array comprises a plurality of processing element nodes interconnected by a plurality of communications links in the form of a hypercube. Each processing element node has a memory including a plurality of storage locations for storing data, and in addition has a hypercube address. The controller controls the processing element nodes in parallel to enable the transfer of data items in a selected manner among the storage locations of the processing element nodes in a series of communications steps. The controller generates a base communications table and enables the processing element nodes to, in parallel, generate respective processing element node communications schedule tables as a selected function of the base communications table and the respective node's hypercube address. Each processing element node communications schedule table associates, for each of a plurality of iterations, storage locations of the processing element node's memory with a dimension of the hypercube. The controller then enables the processing element nodes to, in parallel in a series of transfer iterations, facilitate the transfer of data between storage locations identified in the processing element nodes' respective processing element node communications schedule tables and communications links of the associated dimension.

REFERENCES:
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patent: 5072371 (1991-12-01), Banner et al.
patent: 5105424 (1992-04-01), Flaig et al.
patent: 5113523 (1992-05-01), Colley et al.
patent: 5170482 (1992-12-01), Shu et al.
patent: 5170484 (1992-12-01), Grondalski
"Optimal Matrix Transposition and Bit Reversal on Hypercubes All-To -All Personalized Communication", Journal of Parallel and Distributed Computing, Alan Edelman, 1991.

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