Controlling cache predictive prefetching based on cache hit rati

Details Controlling cache predictive prefetching based on cache hit rati Controlling cache predictive prefetching based on cache hit rati

1992-03-13

1994-11-22

Robertson, David L.

G06F 1300

Patent

active

053676564

ABSTRACT:
In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address. The cache miss prediction mechanism is adaptively selectively enabled by an adaptive circuit that develops a short term operand cache hit ratio history and responds to ratio improving and ratio deteriorating trends by accordingly enabling and disabling the cache miss prediction mechanism.

REFERENCES:
patent: 5093777 (1992-03-01), Ryan
patent: 5285527 (1994-02-01), Crick et al.
IBM Technical Disclosure Bulletin, vol. 30, No. 2, Jul. 1987 p. 510 "New Context Bit".
1987 IEEE International Conference on Computer Design Oct. 5-8, 1987; "Adaptive Cache Management" pp. 129-132.
European Search Report for corresponding EPO patent application 93 102 647.0, transmitted in a Communication dated Jun. 14, 1993.

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