Enhanced fast multiplier

Details Enhanced fast multiplier Enhanced fast multiplier

1994-08-26

1996-12-17

Envall, Jr., Roy N.

Boots, shoes, and leggings

G06F 752

Patent

active

055860710

ABSTRACT:
A Wallace-type binary tree multiplier in which the partial products of a multiplicand and a multiplier are produced and then successively reduced using a plurality of adder levels comprised of full and half adders. This reduction continues until a final set of inputs is produced wherein no more than two inputs remain to be added in any column. This final set is then added using a serial adder and a carry lookahead adder to produce the desired product. The additions at each level are performed in accordance with prescribed rules to provide for fastest overall operating speed and minimum required chip area. In addition, the lengths of the serial adder and carry lookahead adder are chosen to further enhance speed while reducing required chip area. A still further enhancement in multiplier operating speed is achieved by providing connections to adders so as to take advantage of the different times of arrival of the inputs to each level along with different adder input-to-output delays.

REFERENCES:
patent: 5072419 (1991-12-01), Zyner
patent: 5142490 (1992-08-01), Tsujihashi et al.
patent: 5146421 (1992-09-01), Adiletta et al.

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