Process for fabricating complementary vertical transistor memory

Details Process for fabricating complementary vertical transistor memory Process for fabricating complementary vertical transistor memory

1988-10-31

1991-01-01

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 55, 437909, 437915, 437 52, 148DIG72, 148DIG87, 148DIG11, 148DIG109, H01L 2120, H01L 21331

Patent

active

049818074

ABSTRACT:
A compact complementary transistor switch (CTS) memory cell structure utilizing both vertical PNP and vertical NPN transistors in gallium arsenide technology is described. The base region of the vertical PNP transistor merges with the collector region of the vertical NPN transistor. The collector region of the vertical PNP transistor merges with the base region of the vertical NPN transistor. The emitter of the vertical PNP transistor is at the top, and the emitter of the vertical NPN transistor is at the bottom in relation to the emitter of the vertical PNP transistor. This structure leads to improvements in memory density, performance and wireability of a memory array comprising many such cells. A novel yet simple process for making such compact CTS memory cells is also disclosed.

REFERENCES:
patent: 3939039 (1976-05-01), Bonis et al.
patent: 4122482 (1978-10-01), Bonis et al.
patent: 4274891 (1981-06-01), Silvestri et al.
patent: 4482906 (1984-11-01), Hovel et al.
patent: 4483726 (1984-11-01), Isaac et al.
patent: 4485552 (1984-12-01), Magdo et al.
patent: 4573064 (1986-02-01), McLevige et al.
patent: 4586071 (1986-04-01), Tiwari
patent: 4593305 (1986-06-01), Kurata et al.
patent: 4617724 (1986-10-01), Yokoyama et al.
patent: 4625223 (1986-11-01), Komatsubara et al.
patent: 4635087 (1987-01-01), Birrittella et al.
patent: 4649411 (1987-03-01), Birrittella
patent: 4771013 (1988-09-01), Curran
patent: 4807008 (1989-02-01), Chang et al.
A 1024-Byte ECL Random Access Memory Using a Complementary Transistor Switch (CTS) by J. A. Dorler et al., pp. 126-134, IBM's Research Develop, vol. 25; No. 3.

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