Method and apparatus for performing parallel zero detection in a

Details Method and apparatus for performing parallel zero detection in a Method and apparatus for performing parallel zero detection in a

1993-11-29

1994-11-22

Mai, Tan V.

Boots, shoes, and leggings

364784, G06F 700, G06F 750

Patent

active

053674774

ABSTRACT:
A zero detection method (FIG. 5) and a zero detection apparatus (FIGS. 2-4) involves determining if the sum of at least two operands and a carry-in bit will produce a zero result. The zero detection is performed in parallel to another system calculation, such as an addition or subtraction of the two operands. The zero detection logic has a hierarchical structure (see FIG. 4) which is used to reduce logic and quicken the zero detect process of FIG. 5. Zero detection may occur for more than one group of bits within the two operands. The zero detection is used, in a preferred form, primarily in floating point operations such as floating point additions.

REFERENCES:
patent: 3983382 (1976-09-01), Weinberger
patent: 4815019 (1989-03-01), Bosshart
patent: 4878189 (1989-10-01), Kawada
patent: 5020016 (1991-05-01), Nakano et al.
patent: 5091874 (1992-02-01), Watanabe et al.
patent: 5270955 (1993-12-01), Bosshart et al.

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